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National Repository of Grey Literature 2 records found  Search took 0.00 seconds. 
Functional Verification of Processor Execution Units
 Valach, Lukáš ; Lengál, Ondřej (referee) ; Masařík, Karel (advisor)
The thesis deals with integration of functional verification into the design cycle of execution units in  a hardware-software co-design environment of the Codasip system. The aim of the thesis is to design and implement a verification environment in SystemVerilog in order to verify automatically generated hardware representation of the execution units. In the introduction, advantages and basic methods of functional verification and principles of the Codasip system are discussed. Next chapters describe the process of design and implementation of the verification environment of arithmetic-logic unit as well as the analysis of the results of verification. In the end, a review of accomplished goals and the suggestions for future development of the verification environment are made.
Detailed record
Functional Verification of Processor Execution Units
 Valach, Lukáš ; Lengál, Ondřej (referee) ; Masařík, Karel (advisor)
The thesis deals with integration of functional verification into the design cycle of execution units in  a hardware-software co-design environment of the Codasip system. The aim of the thesis is to design and implement a verification environment in SystemVerilog in order to verify automatically generated hardware representation of the execution units. In the introduction, advantages and basic methods of functional verification and principles of the Codasip system are discussed. Next chapters describe the process of design and implementation of the verification environment of arithmetic-logic unit as well as the analysis of the results of verification. In the end, a review of accomplished goals and the suggestions for future development of the verification environment are made.
Detailed record

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